In the semiconductor industry, increasing circuit density drives progress toward smaller and smaller dimensions and larger numbers of transistors placed in an individual device. The challenge to interconnect these transistors becomes increasingly difficult. Some of the problems faced with denser interconnections are increased heat dissipation, greater power consumption, and longer signal delays resulting from higher resistance in the interconnects. The need for smaller dimensions led the industry to develop the dual damascene process. The dual damascene process involves etching a pattern of trenches and holes in a dielectric layer of a semiconductor and subsequently depositing a metal to fill the pattern. A chemical mechanical polishing (CMP) step is then used to planarize the surface before the next layer of dielectric material is deposited and patterned. The filled trenches form the metal interconnect lines and the filled holes form the contact vias which connect the various metal layers to one another.
The development of the dual damascene process allowed the industry to develop devices with high aspect ratio features as well as to develop devices with copper, rather than aluminum, as the interconnect metal. One of the difficulties with fabricating such high aspect ratio interconnect structures is the barrier material, which is employed to encapsulate the metal conductor to prevent diffusion into the surrounding semiconductor materials, must be deposited in such a way as to form a continuous layer on the sidewalls of the trenches and vias. Typical barrier materials used are Ta, TiN, TaN, WN, etc. The current methods of depositing such barrier thin films are Physical Vapor Deposition (PVD), Ionized Physical Vapor Deposition (iPVD), and Chemical Vapor Deposition (CVD). The current methods of depositing the copper interconnect metal further require a copper seed layer to be deposited before the subsequent filling of the trenches and vias with electroplated copper.
Depositing these barrier materials and copper seed layers into high aspect ratio, sub-quarter micron vias and trenches often result in uneven thicknesses at the top of the structure, on the side walls and on the bottom of the structure. These effects result in at least three distinct problems that negatively influence the performance of the semiconductor device. First, an excessive overhang of material at the top of the trench or via may cause a “necking in” of the opening which may restrict or prohibit subsequent thin film depositions and/or filling of the structure with the interconnect metal. This problem may then result in voids in the interconnect metal and thus failed devices. Second, a poor sidewall coverage, especially near the bottom corners of the structure, results in too thin of a barrier material layer to prevent copper diffusion and/or too thin of a copper seed layer to allow subsequent copper electroplating and thus failed devices. Third, a build up of material at the bottom of the trenches or vias due to excessive barrier thin film deposition may cause the structures to have substantially higher intrinsic resistivities (typically 100–1000 micro-Ohm-cm) compared to the interconnect metals (1.7 to 3.5 micro-Ohm-cm). This problem results in a significantly higher contact resistance for the interconnect metal and thus negatively influences the performance/speed of the device.
The use of a GCIB for etching or cleaning planar material surfaces is known (see for example, U.S. Pat. No. 5,814,194, Deguchi et al.) in the art. For purposes of this discussion, gas clusters are nano-sized aggregates of materials that are gaseous under conditions of standard temperature and pressure. Such clusters typically consist of aggregates of from a few to several thousand molecules loosely bound to form the cluster. The clusters can be ionized by electron bombardment or other means, permitting them to be formed into directed beams of known and controllable energy. The larger sized clusters are often the most useful because of their ability to carry substantial energy per cluster ion, while yet having only modest energy per molecule. The clusters disintegrate on impact, with each individual molecule carrying only a small fraction of the total cluster energy. Consequently, the impact effects of large clusters are substantial, but are limited to a very shallow surface region. This makes ion clusters effective for a variety of surface modification processes, without the tendency to produce deeper subsurface damage characteristic of monomer ion beam processing.
Means for creation of and acceleration of such GCIBs are described in the reference (U.S. Pat. No. 5,814,194) previously cited. Presently available ion cluster sources produce clusters ions having a wide distribution of sizes, n (where n=the number of molecules in each cluster—in the case of monatomic gases like argon, an atom of the monatomic gas will be referred to as a molecule and an ionized atom of such a monatomic gas will be referred to as a molecular ion—or simply a monomer ion—throughout this discussion).
It is therefore an object of the present invention to provide a method of opening or widening the top of a trench or via structure which has an excessive overhang of material after barrier material and/or seed material deposition without significantly damaging or degrading the integrity of the remaining material in order to allow subsequent thin film deposition and/or filling of the structure.
It is also an object of the present invention to provide a method of effectively and efficiently redistributing the barrier and/or seed material from the thicker areas in the trench or via, usually the top or bottom of the structure, to the sidewalls without significantly damaging or degrading the integrity of the material in order to provide a more uniform, continuous thin film coverage of the structure.
It is a further object of the present invention to provide a method of fabricating a semiconductor device which reduces the voids present in the metal interconnect lines and/or contact vias thereby increasing the device fabrication yields.
It is a further object of the present invention to provide a method of efficiently fabricating a semiconductor device which allows for the recovery of failed devices due to an excessive overhang of material at the opening of trenches and vias after barrier material and/or copper seed material deposition.